DPR1005/DPR2005 harman/kardon
21Right
32LeftCONSUMER
42Right
53Left
63Right
74Left
84Right
TABLE 13: SDI Input to Channel Mapping (Continued)
4.2.3 ZONE 2 DIGITAL INPUTS
Z2_MCLKZone 2 Master System Clock
This pin is the master clock input for Zone 2. The master clock must be an integer multiple of the
Z2_LRCLK frequency. The default master clock is 12.288 MHz which corresponds to a 48 kHz sample
rate (Fs) * 256. Z2_MCLK is required if the second zone featured is enabled. The Z2_MCLK is a 3.3 volt
input.
Z2_LRCLKZone 2 Left/Right Clock
This pin is the framing clock of the serial data input for Zone 2. The serial input data is transmitted as two
channels every sample rate period. The Z2_LRCLK determines the start of each data pair. The
Z2_LRCLK frequency determines the input sample rate (Fs).The Z2_LRCLK is a 3.3 volt input.
Z2_SCLKZone 2 Shift Clock
This pin is the Shift Clock input for Zone 2. The serial clock is used to frame each input bit of the serial
input data. The shift clock frequency is typically 64*Fs. The Z2_SCLK is a 3.3 volt input.
Z2_SDIZone 2 Serial Data Input
This pin is the Serial Data input for Zone 2. Serial Digital Data is arranged as a single left/right input. The
2
input format options are IS, Left Justified, and Right Justified. 16, 18, 20, and 24 bit data lengths are
available. The Z2_SDI is a 3.3 volt input.
ChannelZONE 2 SDI InputLeft or Right
11Left
21Right
TABLE 14: Z2_SDI Input to Channel Mapping
4.2.4 DIGITAL AUDIO OUTPUTS
LRCLKOOutput Left/Right Clock
This pin is the framing clock for the serial data for the primary channels on SDO[4:1]. The serial output
data is transmitted as two channels every sample rate period. The LRCLKO determines the start of each
data pair. The LRCLKO frequency determines the input sample rate (Fs).The LRCLKO is a 3.3 volt
output.
SCLKOOutput Shift Clock
This pin is the Shift Clock output for the primary channels on SDO[4:1]. The serial clock is used to frame
each input bit of the serial output data. The shift clock frequency is typically 64*Fs. The SCLKO is a 3.3
volt output.
SDO[4:1]Serial Data Output
These pins provide the Serial Data Output for primary Channels. Serial Data is arranged as four left/right
outputs. The SDO is a 3.3 volt output. Note that although input channel 8 does not map to a speaker
output, the results of processing channel 8 may be output on SDO[4].
ChannelSDO OutputsLeft or Right
11Left
21Right
32Left
TABLE 15: SDO Output to Channel Mapping
13
GR70 Data Sheet Aug 26, 2003 v1.82
46 |
ACEC
